1. Field of the Invention
The present invention relates to an active matrix type display apparatus using a display element, specifically, an electroluminescent element (hereinafter, referred to as an EL element) to emit light by injecting a current for displaying an image an image display and the driving method thereof. Hereinafter, in the present specification, the active matrix type display apparatus using the EL element is referred to as an EL panel.
2. Description of the Related Art
<Active Matrix Type Display Apparatus>
FIG. 8 shows a whole configuration example of a color EL panel. The color EL panel shown in the figure includes a display region 2 disposed with a pixel circuit 1 including a display element (an EL element) and a driving circuit thereof as well as a column control circuit 3, a column register 5, a row register 6 and a control circuit 9.
The display region 2 is disposed with a plurality of pixel circuits 1 in a matrix shape along row and column directions. Each pixel circuit 1 is connected with a signal line 4 and a scanning line 7 of the corresponding column. The pixel circuit 1 of the column is loaded with a display signal supplied simultaneously to the corresponding signal line 4 (row selection period) by a control signal (scanning signal) of the scanning line 7. When the scanning signal moves to the next row, the display element contained in each pixel circuit 1 is lighted up in luminance corresponding to the loaded display signal (lighting period). The pixel circuit 1, to perform a color display, includes three sets having a display element of RGB primary colors.
The scanning signal of each scanning line 7 is generated by a row clock KR and a row register 6 having register blocks as many as rows input with a column scanning start signal SPR. The display signal of each column supplied to each signal line 4 is generated by the column control circuits 3 as many as columns. Corresponding to the display element of RGB primary colors disposed for every three columns, the column control circuit 3 includes three sets of the display element. In the column control circuit 3 of each column, a desired display signal is supplied to the signal line 4 of each column by a video signal VIDEO and a sampling signal SP as well as a horizontal control signal 8. A control circuit 9 is input with a horizontal synchronization signal SC corresponding to the video signal VIDEO 9, and generates a horizontal control signal 8. The sampling signal SP is generated by the column resister 5 made of ⅓ number of registers of the column control circuit 3. The column resistor 5 is input with a column clock KC and a column scanning start signal SPC, and the horizontal control signal 8 for mainly performing a reset operation of the column register 5.
<Pixel Circuit>
For the pixel circuit 1, a current writing type endurable to the characteristic variations of a TFT (a thin film transistor) element being used is commonly employed. In this case, a display signal supplied to the signal line 4 is a current signal. The pixel circuit 1 of the display panel is usually formed of the TFT. Since the TFT is great in the characteristic variations, the current writing type endurable to the characteristic variations is often used.
FIGS. 9 and 10 are configuration examples of the pixel circuit of the current writing type (referred to also as [current programming system]) disclosed in each of U.S. Pat. Nos. 6,373,454 and 6,661,180. The pixel circuit 1 shown in the figures includes the EL element (EL in the figures) which is the display element and the drive circuit of the EL element. The drive circuit, in the example of the figures, contains switching transistors (hereinafter, referred to as transistor) M1, M2 and M4 made of an n-type TFT, a drive transistor M3 made of a p-type TFT, and a capacitive element (capacitor) C1.
The pixel circuit 1 is connected with a emission power line PVdd, a signal line “data” for supplying a current “Idata”, and scanning lines P1 and P2 (a first scanning line and a second scanning line) for supplying scanning signals, and a current writing operation and a lighting operation are performed through the driving circuit of the EL element. The EL element has an anode terminal (a current injection terminal) connected to the emission power line PVdd (a first power source) through the transistor M4 and the drive transistor M3, and has the cathode terminal connected to a grounding line (a second power source) CGND.
FIG. 11 shows a time chart of each scanning signal of the scanning lines P1 and P2.
First, at the current writing operation time (row selection time T1), each scanning signal becomes P1=H level and P2=L level, and the transistors M1 and M2 are turned on, and the transistor M4 is turned off. Then, the drive transistor M3 has a drain terminal isolated from a current injection terminal (anode terminal in the examples of FIGS. 9 and 10) of the EL element. In this state, the drive transistor M3 has a gate terminal connected to the signal line “data”, and at the same time, has the gate terminal and the drain terminal short-circuited, thereby being put into a diode connection state. As a result, by the current “Idata” supplied to the signal line “data”, the gate voltage decided by the characteristic of the drive transistor M3 is generated, and is charged to a capacitive element C1 between the gate terminal and the source terminal.
Next, at the lighting operation time (lighting period T2), each scanning signal becomes P1=L level and P2=H level, and the transistors M1 and M2 are turned off, and the transistor M4 is turned on. Then, the drive transistor M3 has a drain terminal connected to a current injection terminal (an anode terminal in the examples of FIGS. 9 and 10) of the El element. In this state, the drive transistor M3 has a gate terminal isolated from the signal line “data”, and is put into an open state, and therefore, at the current writing operation time, the voltage charged to the capacitive element C1 between the gate terminal and the source terminal becomes a gate voltage of the transistor M3 as it is. As a result, the current flowing through the drive transistor M3 becomes approximately the current “Idata” of the signal line “data”, and therefore, the EL element can light up by emission brightness according to the current “Idata”.
When the pixel circuit shown in FIG. 9 is actually formed on the substrate as a display panel, as shown in FIG. 12, each pixel circuit is accompanied by parasitic capacitances cx1 and cx4 respectively by a wire crossing of the scanning lines P1 and P2 and the signal line “data”. Further, for a high-definition display panel, a top emission system that takes out light from above the pixel circuit is commonly adopted. For this reason, the signal line “data”, in the regions superposed with the anode electrode of the EL element and not superposed with the anode electrode, is superposed with a cathode transparent electrode deposited on the whole display region, and thus, parasitic capacitances cx2 and cx3 are accompanied, respectively. Other than these parasitic capacitances, the signal line “data” is accompanied by a capacitance cx5 between a control terminal (a gate terminal) and a main conductive terminal (a source or a drain terminal) of the transistor M2.
The parasitic capacitance accompanying the signal line “data” of each column becomes a total sum of the parasitic capacitance accompanying the pixel circuit of each column. The parasitic capacitance value accompanying this signal line depends on a panel size and the number of displays. For example, in the display panel of 3 inches by 480 rows, the parasitic capacitance value becomes approximately 5 pF. In the pixel circuit of FIG. 10 also, the parasitic capacitance accompanying this signal line becomes approximately the same.
However, the current writing operations of the pixel circuits shown in FIGS. 9 and 10 are greatly affected by the parasitic capacitance. A current writing operating ability (PRG ability) is approximately shown in the following formula (1).[PRG ability]=[writing current]×[writing time]÷[signal line parasitic capacitance]  (1).Unless this [PRG ability] value is secured, a normal current writing operation cannot be realized due to the characteristic variation of the TFT element in which the pixel circuit is generally formed. For that reason, a display image quality is remarkably deteriorated. Particularly, the display image quality of a low brightness small in writing current is deteriorated, and at the same time, a contrast ratio which is an important factor of the image quality cannot be increased. To increase the [PRG ability], the [signal line parasitic capacitance] is almost decided by the number of display rows and a display size, and a substantial reduction cannot be expected, and at the same time, the [writing time] also cannot be increased because of the maintenance of a refresh rate of the display image.
Further, in the pixel circuits shown in FIGS. 4 and 5, the writing current and the drive current are approximately the same. The drive current injected to the EL element cannot be increased when not controlled during the emission period by the scan line P2 to decide the display image, and therefore, the writing current also cannot be increased. Even when controlled during the emission period, an instantaneous light amount of the EL element is increased, and therefore, the writing current cannot be increased when taking into consideration brightness degradation which is a major problem of the EL element.